Method for fabricating ldmos with self-aligned body

ABSTRACT

A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.15/279,190 filed on Sep. 28, 2016, which is incorporated herein in itsentirety.

TECHNICAL FIELD

The present invention generally relates to semiconductor devices, andmore particularly but not exclusively relates to methods for fabricatingLaterally Diffused Metal Oxide Semiconductor (LDMOS) devices.

BACKGROUND

In the fabrication of LDMOS power transistors as part of an integratedcircuit manufacturing process, for performance and cost reasons, it isdesirable for power transistors to be as small as possible. For costreasons, it is also desirable to minimize the number of photomaskingsteps in the manufacturing process.

A prior art integrated LDMOS transistor is shown in cross-section inFIG. 1. Power LDMOS transistors are usually laid out in stripes withvery large width with source and drain stripes alternating. The activearea of the LDMOS is the product of the total width and the Halfpitch,which, the Halfpitch as shown in FIG. 1, is the distance between thecenter of the source stripe and the center of the drain stripe.

Heavily doped N+ and P+ regions are fabricated in the source stripes tocontact the source and body, respectively. Under the N+ and P+ regions,there is a p-type shallow body region. The side-diffusion of this regionunder the gate polysilicon defines the channel of the LDMOS. Theimplants forming this region are shallow enough that the gatepolysilicon could form an effective implant blocker, meaning that theshallow body region can be self-aligned to the polysilicon edge.

There also needs to be a p-type deep body region within the sourcestripe. This deep body region increases the radius of curvature of thebody to drain junction and reduces the electrical resistance of the bodyregion under the N+ source, thereby prevents the turn-on of a parasiticNPN transistor under high drain voltage conditions, which could causedevice destruction.

Since the deep body implants must have a projected range of up toapproximately 0.5 um, the gate polysilicon of the LDMOS, which istypically 0.1-0.3 um thick, is not enough to block the deep implants.Therefore the deep body region must be defined by its own photomaskingstep, using a photoresist layer at least 0.8 um thick. This photomaskingstep can be done either before the poly gate definition (as in thesimplified process flow of FIG. 2a ) or after poly gate definition (asin FIG. 2b ). Either way, since the deep body and gate polysilicon aredefined by two different masks, there will be a misalignment betweenthem which varies from wafer to wafer and site to site on the samewafer. If the deep body implants overlap the poly gate, thresholdvoltage of the LDMOS will increase by an amount dependant on theoverlap. To avoid large variation of threshold voltage, the deep bodymask opening must be spaced inside the source opening by an amountlarger than the side-diffusion of the deep implants plus the maximummisalignment between the masks. This increases the minimum size of thesource/body region.

Another way to produce a device with acceptably low threshold voltagevariation would be to overlap the deep body implants and the poly gateby an amount much larger than the maximum misalignment. This has thedisadvantage of increasing the channel length and halfpitch of thedevice.

From the foregoing discussion it can be concluded that an inventionwhich reduces the area of the source/body region (and hence the LDMOS)while not increasing the total number of photomasking steps would beuseful to a manufacturer of power integrated circuits.

SUMMARY

The embodiments of the present invention are directed to a method forfabricating an LDMOS device, comprising: forming a semiconductorsubstrate; forming a dielectric layer atop the semiconductor substrate;forming an electric conducting layer on the dielectric layer; forming afirst photoresist layer on the electric conducting layer; patterning thefirst photoresist layer through a first mask to form a first opening;etching the electric conducting layer through the first opening;implanting dopants of a first doping type into the semiconductorsubstrate through the first opening, to form a first body regionadjacent to the surface of the semiconductor substrate, and a secondbody region located beneath the first body region; removing the firstphotoresist layer; etching the electric conducting layer using a secondphotoresist layer and a second mask.

The embodiments of the present invention are also directed to an LDMOSdevice fabricated in a semiconductor substrate. The LDMOS devicecomprises: a gate oxide region formed atop the semiconductor substrate;a gate polysilicon region formed on the gate oxide region; a first bodyregion of a first doping type formed in the semiconductor substrate,wherein the first body region is located at a first side of the gatepolysilicon region and adjacent to the surface of the semiconductorsubstrate; a second body region of the first doping type formed beneaththe first body region; a source region of a second doping type formed inthe first body region; a drain region of the second doping type formedin the semiconductor substrate and at a second side of the gatepolysilicon region; wherein the gate polysilicon region, the first bodyregion and the second body region are defined by the same mask and areself-aligned.

The embodiments of the present invention are further directed to amethod for fabricating an LDMOS device, comprising: forming asemiconductor substrate; forming a gate oxide layer atop thesemiconductor substrate; forming a gate polysilicon layer on the gateoxide layer; etching the gate polysilicon layer using a first mask;implanting dopants of a first doping type into the semiconductorsubstrate using the first mask, to form a first body region adjacent tothe surface of the semiconductor substrate, and a second body regionlocated beneath the first region; etching the gate polysilicon layerusing a second mask to form a gate region of the LDMOS; forming a sourceregion of a second doping type in the first body region which is locatedat one side of the gate region; and forming a drain region of the seconddoping type in the semiconductor substrate at the other side of the gateregion.

BRIEF DESCRIPTION OF THE DRAWING

The present invention can be further understood with reference to thefollowing detailed description and the appended drawings, wherein likeelements are provided with like reference numerals. The drawings areonly for illustration purpose, thus may only show part of the devicesand are not necessarily drawn to scale.

FIG. 1 shows a prior art LDMOS.

FIGS. 2a and 2b are simplified process flowcharts outlining two possiblemanufacturing processes that could be used to fabricate the device ofFIG. 1.

FIG. 3 illustrates a sectional view of an LDMOS 300 with self-alignedbody in accordance with an embodiment of the present invention.

FIG. 4 is a simplified process flowchart outlining a method forfabricating LDMOS in accordance with an embodiment of the presentinvention.

FIGS. 5a-5i illustrate the LDMOS at various stages of fabrication usingthe fabricating method shown in FIG. 4.

FIG. 6 illustrates a sectional view of an LDMOS 600 in accordance withanother embodiment of the present invention.

FIG. 7 illustrates a sectional view of an LDMOS 700 with trench sourcecontact in accordance with yet another embodiment of the presentinvention.

DETAILED DESCRIPTION

Reference will now be made in detail to the preferred embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thepreferred embodiments, it will be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone of ordinary skill in the art that the present invention may bepracticed without these specific details. In other instances, well-knownmethods, procedures, components, and circuits have not been described indetail so as not to unnecessarily obscure aspects of the presentinvention.

The terms “left,” right,” “in,” “out,” “front,” “back,” “up,” “down,“top,” “atop”, “bottom,” “over,” “under,” “beneath,” “above,” “below”and the like in the description and the claims, if any, are used fordescriptive purposes and not necessarily for describing permanentrelative positions. It is to be understood that the terms so used areinterchangeable under appropriate circumstances such that embodiments ofthe technology described herein are, for example, capable of operationin other orientations than those illustrated or otherwise describedherein.

In prior generations of LDMOS transistors as shown in FIG. 1, the gatepolysilicon and the deep p-type body implants in the center of thesource/body region are defined by two different masks. To ensureacceptably small variation of threshold voltage and on-resistance, thegate polysilicon and the deep p-type body implants must either be spacedapart or overlap by a distance greater than the maximum misalignmentbetween the masking layers. These solutions have a penalty of largesource opening, long poly width, or high on-resistance. LDMOS devicesaccording to embodiments of the present invention use the same mask forpoly etch and deep body implants, therefore reduce minimum sourceopening size and variation in threshold voltage and on-resistance.

FIG. 3 shows an LDMOS 300 in accordance with an embodiment of thepresent invention. The LDMOS 300 is formed in a semiconductor substrateconsisting of a P type original substrate 320, an N+ Buried Layer (NBL)319 and an N-well 318. The semiconductor substrate may have othercircuits or devices, such as BJT and CMOS, integrated in it. In someembodiments, the semiconductor substrate may have other configurations.For example, the N+ Buried Layer is optional and could be omitted. Andinstead of being formed directly in the original substrate 320, theN-well 318 may be formed in an N type epitaxial layer which is depositedon the original substrate 320. Furthermore, there could further be ap-type “Resurf” layer under the N-well 318.

The LDMOS 300 includes a drain region 311, a gate polysilicon region312, a gate oxide region 313, a source region 314, a body contact region315, a shallow body region 316 and a deep body region 317. The LDMOS 300is usually laid out in stripes with very large width, with source anddrain stripes alternating. Normally, there is gate seal oxide formedatop and at the sidewall of the gate polysilicon region 312. But itcould be omitted or replaced by other structures in some otherembodiments.

Heavily doped source region 314 and body contact region 315 are bothfabricated in the shallow body region 316 to provide good ohmic contact.Usually they are disposed as in FIG. 3, with a P+ stripe in the middleand N+ stripes on both sides. However, other arrangements, for examplewith N+ and P+ alternating in the width direction, are possible.

Compared with the prior art shown in FIG. 1, the gate polysilicon etch,the shallow body implants and the deep body implants in the LDMOS 300are all defined by the same mask, thus the gate polysilicon region 312,shallow body region 316 and deep body region 317 are “self-aligned”. Bydoing so, the LDMOS 300 provides a roughly vertical body/drain junctionbelow the edges of the gate polysilicon region 312.

The process flow used to create the structure is outlined in FIG. 4, andcross-sections of the LDMOS 300 at various stages of fabrication areshown in FIGS. 5a -5 i.

Up until gate polysilicon definition, the process flow is similar toprior art shown in FIG. 2b . The frontend processing may comprisepreparing an original substrate 320, forming N+ buried layer 319,defining active area and forming N-well 318, as illustrated in FIG. 5a .Then, as illustrated in FIG. 5b , a top surface of the semiconductorsubstrate is oxidized to form a gate oxide layer 313. Next, in FIG. 5c ,polysilicon is deposited to form a gate polysilicon layer 312 which islater patterned as a gate by etching. It is well known in the art thatthe gate oxide layer 313 is used as a dielectric layer and the gatepolysilicon layer 312 is used as an electric conducting layer, and maybe replaced by other proper materials.

Unlike the prior art, before gate polysilicon etch, the body definitionstep is done through a photoresist layer 321. As shown in FIG. 5d , aphotoresist layer 321 is formed on the gate polysilicon layer 312 andthen patterned using a body mask to form a source opening. All otherregions of the wafer are covered with photoresist. This step must usethick photoresist, so that the combined thicknesses of the gatepolysilicon layer 312 and the photoresist layer 321 are enough to blockthe highest-energy deep body implant.

Subsequently, this photoresist layer 321 is used to etch the gatepolysilicon layer 312, as shown in FIG. 5e . Then, without removing thephotoresist layer 321, the deep and shallow body implants (acceptor ionssuch as boron and indium) are done through the source opening asillustrated in FIG. 5 f.

After removal of the photoresist layer 321, a second photoresist layer322 is deposited and then patterned using a gate poly mask, as shown inFIG. 5g . This photoresist layer 322 is used to etch the other side ofthe gate polysilicon. After removal of the photoresist layer 322 asillustrated in FIG. 5h , the process continues as usual, including polyseal oxidation, N+ and P+ implantation and activation, silicideformation, contacts, and backend. FIG. 5i shows the LDMOS device incross-section after tungsten plug contact formation.

A rough estimate of the area saving made possible by this invention isnow made. The minimum photoresist opening that can be manufacturably andcost-effectively defined is about one-third of the photoresist thicknessT_block. T_block is defined by the energy of the highest-energy deepbody implant. If the side-diffusion of deep body plus maximummisalignment between gate and deep body masks is d, then the minimumsource opening for the prior art method is approximately:

(T_block/3)+2*d.

For the self-aligned method of the invention, the photoresist thicknesscan be reduced approximately by the thickness T_poly of the gatepolysilicon. The minimum source opening is therefore approximately:

(T_block−T_poly)/3.

Using ballpark values of 0.95 um for T_block, 0.2 um for T_poly, and0.15 um for d, the minimum opening shrinks from 0.62 um to 0.25 um,which is a significant reduction.

Deep body and shallow body implants are combined into one mask usingthis method. Assuming that in the prior art process, the deep body maskis a dedicated mask used only in the LDMOS region, the method of thisinvention reduces the number of photomasking steps in the IntegratedCircuit process by one. This can reduce the wafer cost of the finishedwafer by a non-negligible amount (several percent).

Besides the constraint caused by mask misalignment mentioned above,there is another factor which could also limit the minimum size of thesource opening. That is the minimum opening required to pattern threedistinct heavily doped surface regions (source regions and body contactregion, N+/P+/N+) inside the opening while maintaining strong ohmiccontact to both source and body.

FIG. 6 shows an LDMOS in accordance with another embodiment of thepresent invention, which reduces the area of the source/body region byeliminating the need to pattern butted N+ and P+ regions inside thesource/body region.

The shallow and deep body implants, self-aligned to the gatepolysilicon, span the entire source opening. Implanted after spacerformation (oxide and/or nitride spacers formed at the sidewalls of thegate polysilicon to define the source region), an N+ source implant alsospans the entire source opening. The junction depth of the N+ sourceregion 614 inside the shallow body region 316 is quite shallow,typically on the order of 0.1 um. This is true because directly underthe N+ source, the acceptor concentration is quite heavy to increase theruggedness of the LDMOS.

After silicidation of the gate and drain regions of the LDMOS, apre-metal dielectric layer 623 (also called contact dielectric) isformed. It consists of various doped and undoped deposited oxides,nitrides, oxynitrides, and/or carbides, and isolates the first metallayer from the devices below.

Afterwards, a photoresist layer is formed and a trench contact mask isused to image trench contact openings in the shape of long stripes downthe center of all LDMOS sources. Then the pre-metal dielectric 623 isetched, for example, using a standard contact etch recipe. After that,inside the trench contact openings, silicon is etched away to form atrench with a depth greater than the maximum junction depth of the N+source region 614—typically 0.15-0.2 um. The photoresist is stripped,and then regular contacts are defined and etched. After the regularcontact photoresist is stripped, a contact liner 624 is deposited on thetop of the wafer, covering the edges and bottom of both regular contactsand trench contacts. This contact liner 624 is typically a glue layer oftitanium followed by a barrier layer of titanium nitride. A subsequentrapid thermal anneal step reduces oxygen-containing residues at thebottom of the contacts and makes the contact liner 624 a diffusionbarrier to fluorine in the subsequent tungsten deposition step. Finally,the contacts are completed when they are filled with CVD tungsten, thenpolished back so all tungsten, and all contact liner, are removed fromthe top of the pre-metal dielectric 623. No special silicidation in thetrench contact is required, since both the N+ source region 614 and theshallow body region 316 underneath the N+ source region 614 have highenough concentration so that the titanium of the contact liner forms alow-resistance titanium silicide contact.

The trench source contact solution illustrated in FIG. 6 requires only ablanket N+ region all the way across the source opening, thus reducesthe opening size. Although the trench source contact is fabricated aheadof the regular contacts in the process described above, it is possibleto be done afterwards. Moreover, tungsten which is used to form tungstenplug contacts could also be replaced by other suitable metal.

In practical applications, it may be difficult to remove photoresistfrom small contact openings, so in some embodiments the etch-photoresiststrip-liner deposition-rapid thermal anneal-tungsten CVD-planarizationsequence is repeated twice, once for the trench contacts and once forthe regular contacts.

FIG. 7 shows an LDMOS 700 with trench source contact in accordance withyet another embodiment of the present invention. In the device 700 ofFIG. 7, there is a stepped gate oxide region 713, with thin gate oxidenear the source and a thicker oxide near the drain. For lower-voltagedevices, this is not necessary, and the gate polysilicon can be disposedwholly over thin gate oxide, just as shown in FIG. 3.

In FIG. 7, it further shows a p-type “Resurf” layer 726 underlying theentire active device. The purpose of this p-type region is to depletethe n-type drift region (N well) from the bottom as well as from thesource side, reducing the lateral electric field and thereby increasingthe breakdown voltage. In a Resurf device, the deep body region must bedeep enough to make electrical contact with the p-type Resurf layer 726,which is typically more than 0.5 um deep for breakdown voltages of 20Vand above.

Further referring to the device 700 of FIG. 7, there are shallow N-typeregions 725 which underlap the gate polysilicon region and form theactual source of the LDMOS. These shallow n-type source regions may beimplanted through the same photoresist layer with the shallow and deepbody regions.

It should be known that the doping type for each region in the aboveembodiments may be in an alternating type, for example, the N typeregions may be replaced with P type regions, and vice versa. Moreover,the N type dopants can be selected from one of the following: nitrogen,phosphorus, arsenic, antimony, bismuth and the combination thereof,while the P type dopants can be selected from one of the following:boron, aluminum, gallium, indium, thallium and the combination thereof.

Obviously many modifications and variations of the present invention arepossible in light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described. It should beunderstood, of course, the foregoing disclosure relates only to apreferred embodiment (or embodiments) of the invention and that numerousmodifications may be made therein without departing from the spirit andthe scope of the invention as set forth in the appended claims. Variousmodifications are contemplated and they obviously will be resorted to bythose skilled in the art without departing from the spirit and the scopeof the invention as hereinafter defined by the appended claims as only apreferred embodiment(s) thereof has been disclosed.

What is claimed is:
 1. An LDMOS device fabricated in a semiconductorsubstrate, comprising: a gate oxide region formed atop the semiconductorsubstrate; a gate polysilicon region formed on the gate oxide region; afirst body region of a first doping type formed in the semiconductorsubstrate, wherein the first body region is located at a first side ofthe gate polysilicon region and adjacent to the surface of thesemiconductor substrate; a second body region of the first doping typeformed beneath the first body region; a source region of a second dopingtype formed in the first body region; a drain region of the seconddoping type formed in the semiconductor substrate and at a second sideof the gate polysilicon region; wherein the gate polysilicon region, thefirst body region and the second body region are defined by the samemask and are self-aligned.
 2. The LDMOS of claim 1, wherein thesemiconductor substrate comprises an original substrate of the firstdoping type and a buried layer of the second doping type formed in theoriginal substrate.
 3. The LDMOS of claim 2, wherein the semiconductorsubstrate further comprises a well of the second doping type formed inthe original substrate.
 4. The LDMOS of claim 2, wherein thesemiconductor substrate further comprises a resurf layer of the firstdoping type formed above the buried layer and contacting the second bodyregion.
 5. The LDMOS of claim 1, wherein the gate oxide region has athin gate oxide near the first side of the gate polysilicon region and athicker gate oxide near the second side of the gate polysilicon region.6. The LDMOS of claim 1, further comprising: a pre-metal dielectriclayer formed on the semiconductor substrate; a trench formed in thepre-metal dielectric layer and the first body region, wherein the trenchis laterally located in the center of the source region and verticallyextends from the surface of the pre-metal dielectric layer towards adepth greater than the maximum junction depth of the source region; acontact liner deposited on the bottom and at the sidewalls of thetrench; and metal filling in the trench.